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Executive PG Certification in AI-Enabled VLSI Design
Architect the Silicon of Tomorrow: From Low-Power RTL to AI-Optimized GDSII.
Start Date
June 2026 (Tentative)
Duration
8 Months | 32 Weeks
Course Fee
₹1.25 Lakhs + GST
No. of Seats Left
32
Credits
18
Program Highlights
The only VLSI Design certification program that offers Executive Alumni Status
Hands-On Practice With 100 Hours Of "Cadence tool access"
Capstone Project Aligned to Industry-Grade Semiconductor Use Cases
AI-Enabled VLSI Design Curriculum focused on Low-Power VLSI & Optimization Techniques
Architect High-Efficiency Designs Focused On Fine-Tuning Low-Power PPA Through Industry-Leading EDA Tools.
About IIT Kharagpur
Established in 1951, IIT Kharagpur is India’s first Indian Institute of Technology and a pioneer of technical education, research, and innovation in the country. Over the decades, it has set the benchmark for engineering excellence, academic rigor, and industry relevance, shaping generations of leaders, technologists, and innovators.
IIT Kharagpur is globally recognized for its cutting-edge research, strong industry collaboration, and interdisciplinary approach to solving complex real-world problems. The institute consistently drives innovation across domains such as electronics, semiconductor technology, computer science, manufacturing, and applied sciences, contributing significantly to India’s technological and economic growth.
Guest Speakers
Narayan Prasad
25+ years in semiconductor chip & system design for consumer and enterprise markets. Expert in Analog/Mixed Signal design, specializing in Power Management and Data Converters. Two-time startup co-founder and automotive tech enthusiast.
Dhanapathy Krishnamoorthy
Demonstrated technical acumen of driving innovation and lead 25+ successful SoCs to productization in multiple foundries like UMC, Global Foundries, Samsung & TSMC from 90nm to 3nm with direct foundry interfacing & IP selection.
Murali Kothandapani
Results-driven Product Management and Technology leader with 23+ years of experience driving complex semiconductor product development and customer solutions across ASIC, Memory, Storage, and Embedded Systems.
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Nirmalya Ghosh
Enterprise engineering executive with deep experience in chip design, memory compiler/GPIO/mixed-signal/StdCell development, CAD & methodology, product and resource management, ecosystem leadership, and corporate strategy.
Swagath Venkataramani
Principal Research Scientist at IBM T.J. Watson Research Center, previously a Research Staff Member at IBM and Research Intern at Microsoft Research. Earned his Ph.D. in Electrical & Computer Engineering from Purdue University.
Rangharajan Venkatesan
Researcher in deep learning hardware, computer architecture, ASIC, and VLSI. Award-winning work in spintronic memories and hardware accelerators; active contributor to leading IEEE conferences, including ISSCC, DAC, and ISLPED.
Sabyasachi Deyati
AI/HPC Workload Performance Architect at Intel. Specialized in AI/HPC workload trace analysis and the development of GPU kernel-based projection models. Specifically, an expert in analyzing AI/HPC workloads to optimize performance and efficiency.
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Hari Ananthan
A Senior Director of Engineering at Qualcomm, specializing in agentic AI for hardware design and the development of advanced tools for RTL design, verification, and synthesis.
The IIT Advantage
Experience Campus Immersion At IIT Kharagpur
Certification From IIT Kharagpur
Receive a Certificate of completion from IIT Kharagpur,
recognizing your achievement.
in Just 8 Months
How You Go From Learning to Orchestrating
Module 1: Verilog & Combinational RTL Foundations
Module 1: Verilog & Combinational RTL Foundations
Digital Design Foundations
Verilog Onboarding + First Verified Module
Combinational Modeling Styles + Decoder Design (QoR Awareness)
Module 2: Sequential RTL & FSM Controllers
Module 2: Sequential RTL & FSM Controllers
Verilog System Design Essentials (Job-Aligned) + Code Experiments
Sequential RTL: DFFs & Counters (ASIC Flow Awareness)
FSM Controllers: Sequence, Vending Machine & Elevator Models
Vivado Flow Literacy
Module 3: Memory Blocks & Datapath Design
Module 3: Memory Blocks & Datapath Design
Memory in RTL: Register File, RAM & FIFO (FPGA + ASIC)
Datapath vs Control Logic
Fixed-Point Arithmetic, Truncation & Approximation Safety
Module 4: Low-Power RTL & AI-Augmented Power Aware Architecture
Module 4: Low-Power RTL & AI-Augmented Power Aware Architecture
Design for power, not just functionality
Power Fundamentals I: 4 Power Types + Activity Tracing
Low-Power Techniques: 6 Key Levers
Power-Aware Architecture Design
Clock Gating Cell RTL (Production-Ready) + Verification
Module 5: FPGA Workflow & Cadence Synthesis Workflow / STA Literacy
Module 5: FPGA Workflow & Cadence Synthesis Workflow / STA Literacy
Bridge FPGA and ASIC thinking
FPGA vs ASIC Synthesis Differences
Cadence Synthesis & STA: Genus + Tempus
TCL Scripting and Optimization Using AI
Module 6: Capstone Kickoff
Module 6: Capstone Kickoff
Capstone Kickoff: (Spec→Architecture) + (Algorithm→RTL Plan)
Capstone Build 1: Controller FSM, FIFOs & Testbench
Capstone Build II: Constraints, QoR Optimization for PPA
Module 7: Physical Design Foun dations
Module 7: Physical Design Foun dations
Cadence P&R Baseline using Innovus
QoR Analysis & Iterative Improvements
RTL to GDS Baseline Run
Module 8: Floorplanning & Power Planning Foundations
Module 8: Floorplanning & Power Planning Foundations
Placement + Congestion Mitigation (Power tie-in)
CTS + Routing Overview (OSS) + Clock Power Intuition
Module 9: RTL → GDSII Deep Dive & Signoff
Module 9: RTL → GDSII Deep Dive & Signoff
Cadence RTL → GDSII Baseline (Canonical Block)
Tool Awareness & Mapping to Open-Source Flows
Floorplanning & Locality (Power & Toggling Awareness)
Placement & Congestion Mitigation
CTS, Routing & Process / Corner Variations
Signoff Literacy: DRC, LVS & UPF Power Intent
Power Analysis & Multi-Knob Optimization (Voltus / Joules)
Module 10: AI-Driven Low Power Co-Optimization
Module 10: AI-Driven Low Power Co-Optimization
ML-Based Architecture Design Space Exploration (DSE)
AI-Guided QoR Tuning Loop
Predictive STA & ECO Recommendations (Bounded)
Congestion & Floorplan Prediction
Module 11: Portfolio & Interview Readiness
Module 11: Portfolio & Interview Readiness
Translate skills into job-ready outcomes
Portfolio Curation & Project Storytelling
Interview Readiness for RTL, PD & AI-EDA Roles
Module 12: Capstone Closure & Commercial Low-Power Methodology Showcase
Module 12: Capstone Closure & Commercial Low-Power Methodology Showcase
Low-Power Methodology Showcase (Cadence-based) - demo + decision memo
Participants will gain hands-on experience with
research-oriented projects along with industry-grade tools
Hardware-Accelerated Audio Signal Processing with Neural Network Classifier
Tiny YOLO-Based Object Detection Accelerator for Edge AI
Accelerator for Optical Flow Estimation and Object Detection for Automated Vehicles
While mastering industry standard tools
By The End, You’ll Be Able To Do All This
This Program is for
Educational Qualification
- B.Tech (4th-year students or graduates)/ M.Tech, B.E/M.E in Electronics, ECE, EE, VLSI, Electrical, Instrumentation, CS, IT, M.E, Minor in Electronics or CS with B.Tech/B.E in any field and allied branches.
- M.Sc: Electronics / Physics / Semiconductor Technology.
- Minimum Academic Requirement: 50% aggregate (or equivalent CGPA).
Technical Readiness
- Basic understanding of digital electronics or programming fundamentals expected.
- Prior exposure to Verilog, RTL, FPGA, or embedded systems is an advantage, but not mandatory.
Work Experience
Currently in 4th Year of BTech/UG program/ PG student/ Graduated Fresher / Working Professional.
Learning Support
A pre-program Bridge Course ensures all learners are technically aligned and Day-1 ready, covering core electronics and VLSI fundamentals.
Qualifying Test
Short aptitude-based qualifying test (technical aptitude test)
Qualifying Test
Short aptitude-based qualifying test (technical aptitude test)
Qualifying Assessment
What You’ll Be Tested On
Duration: 90 minutes
Important Guidelines
Online, MCQ-based
Each section has a time limit and can be attempted only once
Do not refresh or close the browser during the qualifying test
Use latest versions of Chrome/Firefox on desktop/laptop
Keep pen and paper handy for rough work
You’ll receive qualifying test access only after completing registration
Electronics & ECE Graduates
Looking to move beyond theory and labs into production-grade RTL, ASIC physical design, and low-power silicon workflows used in real semiconductor teams.
Software / Embedded Engineers Transitioning to VLSI
Professionals aiming to shift from software or firmware roles into chip design, FPGA prototyping, or AI-enabled EDA workflows.
Early-Career VLSI & FPGA Engineers
Engineers who want signoff-grade exposure to Cadence tools, cloud FPGA, and RTL-to-GDSII flows to become industry-ready faster.
Mid-Career Professionals in Semiconductor Roles
Working professionals seeking to upskill in low-power design, physical design awareness, and AI-driven EDA orchestration for long-term growth in the VLSI ecosystem.
Roles That’ll Be Looking For You
RTL Design Engineer
₹6 – 18 LPA
VLSI Digital Design Engineer
₹6 – 22 LPA
ASIC Design Engineer (Frontend)
₹10 – 28 LPA
SoC Design Engineer (Digital Subsystems)
₹15 – 35 LPA
Micro-Architecture Engineer
₹14 – 32 LPA
Low-Power RTL Design Engineer
₹12 – 30 LPA
Physical Design Engineer (P&R)
₹8 – 25 LPA
Backend ASIC Engineer
₹9 – 28 LPA
Floorplanning Engineer
₹12 – 30 LPA
STA Engineer
₹8 – 24 LPA
CTS & Routing Engineer
₹10 – 26 LPA
Power Analysis & Optimization Engineer
₹12 – 35 LPA
Career Assistance
Profile, Narrative & Resume Building
Craft a recruiter-ready identity with optimized resumes, LinkedIn profiles, and a strong career narrative.
Career-Specific Training
Develop job-ready skills with role-focused training, capability tests, AI tools workshops, and continuous upskilling to match real hiring expectations.
Futurense Job Board - Exclusive Opportunities
Access curated, pre-vetted roles before they hit public portals, with priority visibility for Futurense learners.
Interview Playbooks & Cheat Sheets
Get insider interview guidance with structured playbooks: FAQs, sample answers, frameworks, recruiter insights, and round-wise preparation.
Mock Interviews with Experts
Experience real interview simulations with personalized feedback from mentors, industry leaders, and FLC members.
Mentor Referrals & Networking
Unlock referral advantages, insider recommendations, alumni-driven opportunities, and FLC mentorship that accelerates your career entry.
Salary Negotiation Support
Get guidance on positioning, benchmarking, negotiation strategy, and communication to secure the compensation you deserve.
Our students are acing it!
Disclaimer: All products and company names are trademarks or registered trademarks of their respective holders. Use of product and company names does not imply any affilation with or endorsement by the holders.
They are working at companies which are a dream for most
Fee Structure
Total Admission Fee
₹1,25,000
+18% GST
| Component | Amount (₹) |
|---|---|
| Program Fee | ₹1,20,000 |
| GST (18%) | As applicable |
| Registration Fee (Non-Refundable)* | ₹5,000 (Adjusted in Program Fee) |
| Total Payable | ₹1,25,000 + 18% GST |
The registration fee of ₹5,000 is a one-time, non-refundable application processing fee, adjusted against the total program fee.
Payment of the registration fee is required at the time of application submission.
EMI options are available through partner NBFCs.
If a participant withdraws before the program start date, the program fee will be refunded, excluding:
Registration fee, GST, Any applicable subvention or processing charges.
No refunds are applicable once the program has commenced.
Optional 2-Day Campus Immersion at IIT Kharagpur may be offered at an additional cost (subject to actuals).
Travel, boarding, and lodging expenses for campus immersion (if opted) will be borne by the participant.
Application Deadline
10th April, 2026
Admissions close once the required number of students is enrolled for the upcoming cohort. Apply early to secure your seat.
How it Works
Application Process
1
Submit Your Application
Apply online with your basic details and pay the ₹5,000 non-refundable registration fee to complete your application.
2
Pre-Screening Test
Take a pre-screening test to assess your technical readiness and suitability for the AI-Enabled VLSI Design program.
3
Offer & Begin Your Learning Journey
Receive your offer letter, complete the fee payment, and get immediate access to the Futurense Bridge Course before classes begin.
Traditional VLSI Programs vs. IIT Kharagpur’s AI-Enabled VLSI Design
Dimension
This Programme
Other Programme
Core Philosophy
Production-grade RTL-to-GDSII engineering, focused on low-power, AI-assisted silicon design and real sign-off constraints
Tool-centric or theory-heavy learning with limited exposure to real silicon constraints
Role Orientation
Industry-aligned roles across RTL Design, Physical Design, FPGA, Low-Power & AI-EDA workflows
Academic or entry-level focus without clear mapping to production VLSI roles
Curriculum Design
End-to-end flow: RTL → Synthesis → STA → Physical Design → Sign-off, integrated with AI-EDA
Fragmented modules taught in isolation (RTL, PD, or verification separately)
Learning Style
Industry-standard Cadence tools, FPGA relevant workflows, and AI-guided design space exploration
Lecture-driven learning with simulations and small academic assignments
Production Readiness
Emphasis on PPA trade-offs, timing closure, power intent (UPF), congestion, and sign-off literacy
Limited focus on production realities like timing, power leakage, or closure loops
EDA & Tool Exposure
Industry-standard Cadence tools, cloud FPGA workflows, and AI-guided design space exploration
Local tools, open-source only, or limited exposure to professional EDA environments
AI Integration
AI-assisted EDA workflows for DSE, and QoR tuning
Little to no exposure to AI-enabled design or automation in VLSI
Portfolio Output
Sign-off-ready evidence packs: waveforms, QoR reports, logs and capstone
Academic projects or RTL demos without production-grade artifacts
Feeling Underconfident About Your Skills?
Kick things off with a 2-Week Bridge Course that gets you course-ready
What you'll learn:
Semiconductor Material & Analog Basics
GenAI, Agentic AI and Prompt Engineering
System Thinking for AI
Digital Electronics & HDL Foundations
Worth ₹29,000
Included free with your enrollment.
Led by the Futurense Leadership Council (FLC)
A collective of CXOs, AI leaders, and digital transformation heads from global and Fortune 500 companies shaping the AI-native workforce.
Ready to Design the Next Generation of AI-Optimized Silicon?
Low-power design, and AI-driven EDA are redefining how chips are built. Engineers trained for yesterday won’t make tomorrow’s silicon.
Frequently Asked Questions
We know you might have some questions before getting started in our platform
What is the name of the certification program, and which IIT offers it?
The program is called the Executive Post Graduate Certification in AI-Enabled VLSI Design and it is offered by the Indian Institute of Technology Kharagpur (IIT Kharagpur).
What is the duration of the program, and when does the next cohort begin?
The program duration is approximately 8 months, with the next cohort tentatively scheduled to begin in June 2026.
What are the eligibility criteria for this program, and who should ideally enroll?
Criteria:
1. B.Tech/M.Tech or B.E/M.E (final-year students or graduates).
2. Acceptable disciplines include Electronics, ECE, Electrical Engineering, VLSI, Instrumentation, Computer Science, and IT.
3. M.Sc. in Electronics, Physics, or Semiconductor Technology, or MCA is also accepted.
4. Minimum 50% aggregate marks or equivalent CGPA from a recognized university.
Ideal Candidates:1. 4th-year engineering students interested in VLSI design.
2. Fresh graduates looking to start a career in semiconductor and chip design.
3. Working professionals seeking to transition into VLSI roles.
4. Candidates from other engineering backgrounds with exposure to digital electronics, HDL, embedded systems, or semiconductor fundamentals.
How can I apply to the Executive Post Graduate Certification in AI-Enabled VLSI Design?
Applicants can apply online by completing the application form and submitting their personal, educational, and professional details along with the required documents.
When will the application process for the program start?
The application process has already begun, and candidates can apply while seats are still available.
Is there a selection process?
Yes. The selection process involves submitting an application, a profile review by the technical committee, and a pre-screening test to assess subject knowledge before receiving the final offer letter.
What are the documents to be submitted for the application?
Applicants must submit documents such as Aadhar Card, date of birth proof, resume, graduation marksheets and degree certificates, 12th marksheet, and work experience documents if applicable.
Will there be any pre-screening test for enrolling in the program?
Yes. A pre-screening test evaluates candidates’ understanding of digital electronics, analog electronics, logical reasoning, and Verilog fundamentals.
Should I have experience in coding to qualify for the pre-screening test?
Basic knowledge of Verilog coding is recommended to perform well in the pre-screening test and to start the program smoothly.
How is the teaching format structured for this program?
The program is delivered through 100% live online classes conducted by IIT Kharagpur faculty and industry experts.
Will there be any additional cost for attending the optional 3-day IIT Kharagpur campus immersion?
Yes. Participants who choose to attend the optional campus immersion will need to pay approximately ₹10,000 closer to the immersion dates.
Will hostel accommodation be provided for outstation candidates during immersion?
Yes. Accommodation booking can be facilitated for outstation candidates during the campus immersion, subject to availability.
Why is this program considered unique compared to other certifications in VLSI?
The program integrates industry-grade Cadence tools, the Vivado FPGA workflow, and a complete RTL-to-GDSII design flow enhanced with AI-driven PPA optimization and low-power design techniques.
Who is the program director, and why is their expertise significant?
The program is led by Prof. Mrigank Sharad, whose expertise in nanoelectronics, VLSI design, and digital and mixed-signal systems contributes to developing energy-efficient AI hardware and modern semiconductor technologies.
What makes IIT Kharagpur a trendsetter in technological education, particularly in VLSI?
Established in 1951 as India’s first IIT, IIT Kharagpur has a strong legacy in engineering education and advanced semiconductor research, combining academic rigor with industry-relevant curriculum design.
How do industry leaders contribute to the program?
Industry practices and modern semiconductor workflows are integrated into the curriculum, ensuring that learners gain exposure to real-world design methodologies and AI-enabled chip design practices.
What areas of VLSI design does this program cover?
The curriculum covers digital design foundations, Verilog-based RTL development, FPGA workflows, ASIC implementation, low-power design, and the complete RTL-to-GDSII design lifecycle including timing analysis and physical design.
What tools and platforms are covered in this program?
Participants gain hands-on experience with tools such as Vivado IDE and Cadence tools including Xcelium, Genus, Innovus, Tempus, and Voltus. The program also includes Verilog programming and basic TCL scripting.
What makes the AI integration in this program unique?
The program integrates AI-driven workflows including machine-learning-based design space exploration, predictive static timing analysis, and AI-guided optimization of power, performance, and area metrics.
What makes this certificate program particularly suitable for engineers and tech professionals?
The program offers full-stack exposure from RTL design to GDSII implementation using commercial-grade semiconductor toolchains and AI-enabled automation workflows.
How does the program enable participants to specialize in their specific engineering domains?
Through modular learning and customizable capstone projects, participants can focus on areas aligned with their interests within semiconductor design.
What are some practical projects or hands-on learning outcomes included in the course?
Participants work on projects such as hardware-accelerated audio signal processing with neural network classifiers, Tiny-YOLO based object detection accelerators, and optical flow estimation accelerators for automated vehicles.
What job roles can participants expect to pursue after completing this program?
Graduates can pursue roles such as RTL Design Engineer, FPGA Design Engineer, ASIC Implementation Engineer, Physical Design Engineer, Low-Power Design Specialist, and AI-EDA Integration Specialist.
How does having skills in AI-integrated EDA impact salary and job prospects?
AI-integrated EDA skills are highly valued in the semiconductor industry and open access to specialized roles with higher compensation potential.
Why will this certificate program future-proof careers in a rapidly evolving market?
The program equips learners with both traditional VLSI methodologies and emerging AI-driven automation skills, preparing them for the evolving semiconductor ecosystem.
What certification will I receive upon completion?
Upon successful completion, participants receive the Executive Post Graduate Certification in AI-Enabled VLSI Design from IIT Kharagpur.
What is the program fee, and what financing options are available?
The program fee is ₹1,25,000 plus 18% GST. Financing options are available through partner financial institutions.
What is the payment schedule and process?
A non-refundable application deposit of ₹5,000 must be paid during application submission and is adjusted in the final fee. The remaining fee must be paid within five days of receiving the offer letter.
Can I self-fund this program?
Yes. Participants can self-fund the program either fully or partially through personal or family resources.
Does Futurense help with loans?
Yes. Futurense partners with financial institutions to help eligible participants access loan options.
What is the interest rate on the loans?
Interest rates vary depending on the financial partner and repayment plan and are generally competitive in the current lending market.
What documents should I keep handy for financing?
Applicants should keep their:
1. PAN card.
2. Aadhaar card.
3. Bank statements for the last three months (required for financing or loan processing).